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| JBT6K47-AS Preliminary TOSHIBA CMOS Digital Integrated Circuits Silicon Monolithic JBT6K47-AS Source Driver for TFT LCD Panels The JBT6K47-AS is a 64 gray-level, 240-channel-output source driver for TFT LCD panels. 6-bit digital input enable to display colors using internal DA converter and five external power supplies. Also, JBT6K47-AS incorporates power saving function to control recognition of the grayscale data input. When display performance is not necessary, such as in a portable device, JBT6K47-AS ignores the grayscale input data. Based on high-speed CMOS, the JBT6K47-AS offers both low power consumption and high-speed operation. Features * * * * * * * * * * Grayscale data: 18-bit digital (3 outputs x 6 bits) parallel transfer method, selectable write direction Panel drive outputs: 240 outputs Grayscale levels: Capable of switching 2-grayscale mode and 16 grayscale/64 grayscale mode, and capable of reference analog voltage inputs. High-speed operation: 5 MHz (max) Display mode: Normal display mode Power supply voltage: Digital power supply voltage (DVDD) .............2.5 to 3.6 V Analog power supply voltage (AVDD)..............4.5 to 5.6 V Operating temperature: -20 to 75C Package: Gold bump chip CMOS process Cascading multiple devices 1 2002-01-30 JBT6K47-AS Block Diagram U/D DI/O CPH POL XIN0~5 YIN0~5 ZIN0~5 Shift register DO/I Sampling register XOR operation Load register GS MD Display switching circuit Level shifter LOAD V0~5 Op Amp Data control circuit DW AVDD DVDD AVSS DVSS Output circuit (SW circuit) X01 Z01 Y01 X88 Z88 Y88 2 2002-01-30 JBT6K47-AS PAD Coordinates Item Chip size (1) (2) Chip end coordinates (3) (4) Bump pitch Bump height Size 12600 2350 -6300, 1175 -6300, -1175 6300, -1175 6300, 1175 43 (15) mm mm mm Unit mm Pin Name Input pin Output pin TEG pin DUMMY pin Alignment mark Numbers of Pin 123 (Except dummy pins) 264 (Except dummy pins) 8 38 2 Note 1: The TEG pin is a test pin reserved for electrical characteristics measurements and must be left open. Alignment mark Pattern prohibited Al Coordinates entry value 50 mm 30 mm 30 mm 30 mm 50 mm 50 mm 30 mm 30 mm 50 mm 30 mm 3 2002-01-30 PAD Layout Alignment mark 2 DUMMY23 DUMMY22 DUMMY21 Z88 Y88 X88 Z1 Y1 X1 DUMMY20 DUMMY19 DUMMY18 Output pad 270/43 mm pitch two-step zigzag allocation JBT6K47-AS Chip size: 12.60 2.35 mm 15 DUMMY25 to 38 Alignment mark 1 15 3 3 3 3 3 3 5 3 XIN4 XIN3 XIN2 XIN1 XIN0 DI/O AVSS * Short-side dummy pins 100 50 50 AVDD DUM 3 V4 V3 V2 V1 U/D DO/I ZIN5 ZIN4 ZIN3 ZIN2 ZIN1 ZIN1 GS POL V5 LOAD CPH /TEST1 DVDD /TEST2 DVSS 5 3 3 3 3 3 3 3 3 3 32323 323 3 3 3 3 3 V0 22 3 MD DUMMY DW 3 YIN5 3 YIN4 3 YIN3 3 YIN2 3 YIN1 3 YIN0 * 65 65 65 3 XIN5 * Power supply pins (AVSS) Output pins (X1~Z88) AVDD AVSS * Power supply pins (AVDD, DVDD, DVSS, V0-V5) 40 46 40 70 70 70 70 70 110 110 105 20 20 20 20 20 20 50 40 40 * Input pins (/TEST1, /TEST2, POL, MD) 40 105 40 * Input pins (others) 50 50 50 43 46 JBT6K47-AS PAD Coordinates (1) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 Name AVDD AVDD AVDD AVSS AVSS AVSS AVSS AVSS DO/I DO/I DO/I ZIN5 ZIN5 ZIN5 ZIN4 ZIN4 ZIN4 ZIN3 ZIN3 ZIN3 ZIN2 ZIN2 ZIN2 ZIN1 ZIN1 ZIN1 ZIN0 ZIN0 ZIN0 U/D U/D U/D LOAD LOAD LOAD CPH CPH CPH /TEST1 /TEST1 DVDD DVDD DVDD X POINT Y POINT -5994 -5909 -5824 -5679 -5589 -5499 -5409 -5319 -5171 -5101 -5031 -4911 -4841 -4771 -4621 -4551 -4481 -4361 -4291 -4221 -4071 -4001 -3931 -3811 -3741 -3671 -3521 -3451 -3381 -3261 -3191 -3121 -2971 -2901 -2831 -2711 -2641 -2571 -2404 -2344 -2221 -2136 -2051 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 No. 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 Name /TEST2 /TEST2 DVSS DVSS DVSS GS GS GS POL POL V5 V5 V5 V4 V4 V4 V3 V3 V3 V2 V2 V2 V1 V1 V1 V0 V0 V0 MD MD DUMMY1 DUMMY2 DW DW DW YIN5 YIN5 YIN5 YIN4 YIN4 YIN4 YIN3 YIN3 X POINT Y POINT -1920 -1860 -1737 -1652 -1567 -1409 -1339 -1269 -1154 -1094 -873 -788 -703 -568 -483 -398 -233 -148 -63 72 157 242 407 492 577 712 797 882 1103 1163 1278 1348 1472 1542 1612 1732 1802 1872 2022 2092 2162 2282 2352 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 No. 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 Name YIN3 YIN2 YIN2 YIN2 YIN1 YIN1 YIN1 YIN0 YIN0 YIN0 XIN5 XIN5 XIN5 XIN4 XIN4 XIN4 XIN3 XIN3 XIN3 XIN2 XIN2 XIN2 XIN1 XIN1 XIN1 XIN0 XIN0 XIN0 DI/O DI/O DI/O AVSS AVSS AVSS AVSS AVSS AVDD AVDD AVDD DUMMY3 DUMMY4 DUMMY5 DUMMY6 [Unit: mm] X POINT Y POINT 2422 2572 2642 2712 2832 2902 2972 3122 3192 3262 3382 3452 3522 3672 3742 3812 3932 4002 4072 4222 4292 4362 4482 4552 4622 4772 4842 4912 5032 5102 5172 5321 5411 5501 5591 5681 5824 5909 5994 6146 6146 6146 6146 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -996 -785 -685 -585 -485 5 2002-01-30 JBT6K47-AS PAD Coordinates (2) No. 130 131 132 Name DUMMY7 DUMMY8 DUMMY9 X POINT Y POINT 6146 6146 6146 6146 6146 6146 6146 6146 6146 6146 6146 5784 5741 5698 5655 5612 5569 5526 5483 5440 5397 5354 5311 5268 5225 5182 5139 5096 5053 5010 4967 4924 4881 4838 4795 4752 4709 4666 4623 4580 4537 4494 4451 -385 -285 -185 -85 15 115 215 315 415 515 615 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 No. 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 Name Z10 X11 Y11 Z11 X12 Y12 Z12 X13 Y13 Z13 X14 Y14 Z14 X15 Y15 Z15 X16 Y16 Z16 X17 Y17 Z17 X18 Y18 Z18 X19 Y19 Z19 X20 Y20 Z20 X21 Y21 Z21 X22 Y22 Z22 X23 Y23 Z23 X24 Y24 Z24 X POINT Y POINT 4408 4365 4322 4279 4236 4193 4150 4107 4064 4021 3978 3935 3892 3849 3806 3763 3720 3677 3634 3591 3548 3505 3462 3419 3376 3333 3290 3247 3204 3161 3118 3075 3032 2989 2946 2903 2860 2817 2774 2731 2688 2645 2602 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 No. 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 Name X25 Y25 Z25 X26 Y26 Z26 X27 Y27 Z27 X28 Y28 Z28 X29 Y29 Z29 X30 Y30 Z30 X31 Y31 Z31 X32 Y32 Z32 X33 Y33 Z33 X34 Y34 Z34 X35 Y35 Z35 X36 Y36 Z36 X37 Y37 Z37 X38 Y38 Z38 X39 [Unit: mm] X POINT Y POINT 2559 2516 2473 2430 2387 2344 2301 2258 2215 2172 2129 2086 2043 2000 1957 1914 1871 1828 1785 1742 1699 1656 1613 1570 1527 1484 1441 1398 1355 1312 1269 1226 1183 1140 1097 1054 1011 968 925 882 839 796 753 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 133 DUMMY10 134 DUMMY11 135 DUMMY12 136 DUMMY13 137 DUMMY14 138 DUMMY15 139 DUMMY16 140 DUMMY17 141 DUMMY18 142 DUMMY19 143 DUMMY20 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 X1 Y1 Z1 X2 Y2 Z2 X3 Y3 Z3 X4 Y4 Z4 X5 Y5 Z5 X6 Y6 Z6 X7 Y7 Z7 X8 Y8 Z8 X9 Y9 Z9 X10 Y10 6 2002-01-30 JBT6K47-AS PAD Coordinates (3) No. 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 Name Y39 Z39 X40 Y40 Z40 X41 Y41 Z41 X42 Y42 Z42 X43 Y43 Z43 X44 Y44 Z44 X45 Y45 Z45 X46 Y46 Z46 X47 Y47 Z47 X48 Y48 Z48 X49 Y49 Z49 X50 Y50 Z50 X51 Y51 Z51 X52 Y52 Z52 X53 Y53 X POINT Y POINT 710 667 624 581 538 495 452 409 366 323 280 237 194 151 108 65 22 -21 -64 -107 -150 -193 -236 -279 -322 -365 -408 -451 -494 -537 -580 -623 -666 -709 -752 -795 -838 -881 -924 -967 -1010 -1053 -1096 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 No. 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 Name Z53 X54 Y54 Z54 X55 Y55 Z55 X56 Y56 Z56 X57 Y57 Z57 X58 Y58 Z58 X59 Y59 Z59 X60 Y60 Z60 X61 Y61 Z61 X62 Y62 Z62 X63 Y63 Z63 X64 Y64 Z64 X65 Y65 Z65 X66 Y66 Z66 X67 Y67 Z67 X POINT Y POINT -1139 -1182 -1225 -1268 -1311 -1354 -1397 -1440 -1483 -1526 -1569 -1612 -1655 -1698 -1741 -1784 -1827 -1870 -1913 -1956 -1999 -2042 -2085 -2128 -2171 -2214 -2257 -2300 -2343 -2386 -2429 -2472 -2515 -2558 -2601 -2644 -2687 -2730 -2773 -2816 -2859 -2902 -2945 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 No. 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 Name X68 Y68 Z68 X69 Y69 Z69 X70 Y70 Z70 X71 Y71 Z71 X72 Y72 Z72 X73 Y73 Z73 X74 Y74 Z74 X75 Y75 Z75 X76 Y76 Z76 X77 Y77 Z77 X78 Y78 Z78 X79 Y79 Z79 X80 Y80 Z80 X81 Y81 Z81 X82 [Unit: mm] X POINT Y POINT -2988 -3031 -3074 -3117 -3160 -3203 -3246 -3289 -3332 -3375 -3418 -3461 -3504 -3547 -3590 -3633 -3676 -3719 -3762 -3805 -3848 -3891 -3934 -3977 -4020 -4063 -4106 -4149 -4192 -4235 -4278 -4321 -4364 -4407 -4450 -4493 -4536 -4579 -4622 -4665 -4708 -4751 -4794 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 7 2002-01-30 JBT6K47-AS PAD Coordinates (4) No. 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 Name Y82 Z82 X83 Y83 Z83 X84 Y84 Z84 X85 Y85 Z85 X86 Y86 Z86 X87 Y87 Z87 X88 Y88 Z88 [Unit: mm] X POINT Y POINT -4837 -4880 -4923 -4966 -5009 -5052 -5095 -5138 -5181 -5224 -5267 -5310 -5353 -5396 -5439 -5482 -5525 -5568 -5611 -5654 -5697 -5740 -5783 -6146 -6146 -6146 -6146 -6146 -6146 -6146 -6146 -6146 -6146 -6146 -6146 -6146 -6146 -6146 6054 -6054 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 1015 860 615 515 415 315 215 115 15 -85 -185 -285 -385 -485 -585 -685 -785 940 940 408 DUMMY21 409 DUMMY22 410 DUMMY23 411 DUMMY24 412 DUMMY25 413 DUMMY26 414 DUMMY27 415 DUMMY28 416 DUMMY29 417 DUMMY30 418 DUMMY31 419 DUMMY32 420 DUMMY33 421 DUMMY34 422 DUMMY35 423 DUMMY36 424 DUMMY37 425 DUMMY38 3/4 3/4 Alignment mark 1 Alignment mark 2 8 2002-01-30 JBT6K47-AS Pin Function Pin Name X01 to X88 Y01 to Y88 Z01 to Z88 I/O Function O LCD panel drive pins Data transfer enable pin These pins indicate the input, starting to transfer the grayscale data, and the output, ending to transfer the data. The U/D pin as shown below determines the function. U/D H L DI/O DO/I I/O DI/O Input Output DO/I Output Input When set for input A high on DI/O or DO/I is latched into the internal logic synchronously with the rising edge of CPH. When the internal circuit is in standby state, the device is ready to transfer data. The grayscale data is latched in sequentially, starting at the next rise of CPH. Also, regardless how many rising edges are existed, DI/O or DO/I recognizes the first rising edge, and the grayscale data is latched at the next rising edge. When set for output The pin is used to transfer the enable signal to the JBT6K47-AS at the next stage of the LCD driver. The pin enters standby state after outputting a high. Transfer direction select pin This pin specifys the directions of transfering the grayscale data. Data is transferred synchronously with each rising edge of CPH in one of the following sequences: When U/D is High: X01 to Z01, X02 to Y02, Z03 to Z03, ...... When U/D is Low: X88 to Z88, X87 to Z87, X86 to Z86, ...... The voltage applied to this pin must be a DC-level voltage that is either high or low. U/D I CPH I Data transfer clock pin (Can be stopped except the sampling period) This clock input is used to transfer grayscale data. In sync with the rising edge of CPH, writes grayscale data bus data to the sampling register. Grayscale data input pin An output data consists of six bits, and three output data are latched into the devise simultaneously in one transfer. The POL pin and the result of the operation are written in this data bus. Weighted data bit is shown below. Grayscale data = (32 wIN5) + (16 wIN4) + (8 wIN3) + (4 wIN2) + (2 wIN1) + wIN0 w = X, Y, Z Data load input pin This pin recognizes the High level. The data is transferred from the Sampling register to the Load register asynchronously at the rising edge of CPH, and outputs the corresponded voltage to the grayscale data. Data polarity reversal pin This pin is used to select reversing the grayscale data or not. XIN0 to XIN5 YIN0 to YIN5 ZIN0 to ZIN5 I LOAD I POL I When POL is High: Reversing the grayscale data. When POL is Low: Not reversing the grayscale data. The data is transferred to the internal logic from the timing generator. The grayscale data bus and the operation result of this pin are latched into the internal logic synchronously with the rising edge of CPH. Data control pin This pin is used to forcibly make the grayscale data to High level. DW I 9 2002-01-30 JBT6K47-AS Pin Name I/O Function Grayscale data bus switching pin (Switching display mode) This pin enables to choose the display colors by switching numbers of valid data bus of the grayscale consisted of 6 bits/out. MD GS MD I L L H Note 2: /TEST1 /TEST2 V0 to V5 DVDD AVDD DVSS AVSS I GS H L L Numbers of Valid Bus 6/out 4/out 1/out Gradation Levels 64 levels 16 levels 2 levels Display Colors 26 thousand colors 4096 colors 8 colors When MD = "1", GS = "1", select 4-bit mode (4096 colors) Test pin The pull up resistor is connected to this pin, and must be left open. Power supply pin for grayscale reference voltage (For reference analog voltage inputs) VSS < V0 < V1 < V2 < V3 < V4 < V5 < AVDD or = = = = = = = VSS < V5 < V4 < V3 < V2 < V1 < V0 < AVDD = = = = = = = Digital circuit power supply pin Analog circuit power supply pin Digital circuit GND pin Analog circuit GND pin I 3/4 3/4 3/4 3/4 10 2002-01-30 JBT6K47-AS Device Operation * Starting data transfer A high input to the data transfer enable pin (DI/O or DO/I) is latched into the internal logic synchronously with the rising edge of CPH, setting the device ready to transfer data. Data transfer starts at the next rise of CPH. Also, regardless how many rising edges are existed, DI/O or DO/I recognizes the first rising edge, and the grayscale data is latched at the next rising edge. * Data transfer method The data is latched in from the grayscale bus to the sampling register synchronously with each rising edge of CPH. Grayscale data for three outputs are latched into the device simultaneously in one transfer. Grayscale data are written as three outputs in parallel during one transfer. Data transfer completes after 88 transfers. Then the device enters Standby mode. Data written to the sampling register are the operation result of the grayscale data bus. * Terminating data transfer The data transfer enable pin (DO/I or DI/O) output goes high synchronously with the rising edge of CPH one clock period before the last data is latched in. The output from this pin can be connected directly as input to the data transfer enable pin (DI/O or DO/I) of the next stage LCD driver. In this way, multiple devices can be easily cascaded to drive a large screen. * Panel drive output After finishing transferring the grayscale data, the data is latched into the devise when Load is at High level. The grayscale data of the sampling register is transferred to the load register, and the LCD panel drive output is switched to the corresponded output to the grayscale data. The load signal recognizes the data asynchronously with the CPH. * The grayscale data bus JBT6K47-AS is capable to determine the valid grayscale data bus by controlling MD pin and GS pin. The relationship between the MD pin or the GS pin and the valid grayscale data bus is shown below. Input Low or High for the invalid grayscale data bus. Grayscale Data Bus 6-bit mode 4-bit mode 1 bit mode Valid Grayscale Data Bus nIN5 26 thousand colors 4096 colors 8 colors Valid L/H Valid L/H L/H nIN4 nIN3 Valid L/H L/H L/H L/H nIN2 nIN1 nIN0 MD GS Colors L H L H L n = X, Y, Z Note 3: L/H indicates VDD level or VSS level. : When MD = High, GS = High, the grayscale data bus is set to 4-bit mode. 11 2002-01-30 JBT6K47-AS * Reference power supply circuit The connection between the device and the reference power supply for reference analog voltage inputs is configured with the resistors in series. The reference power supply circuit is capable of impedance transforming the corrected voltage using the Op amp, and the voltage is used for the grayscale level power supply of the internal circuit. (Total of 32 resistor ladders) (Note 4) /VLC V0 R0 R1 V1 External power supply for reference voltage (JBT6K49-AS is recommended) JBT6K47-AS V2 V3 R3 wIN0 (LSB) R4 V4 VLC V5 Note 4: When correction is needed, connect the correction resistor between VLC terminal and /VLC terminal of JBT6K49-AS, and apply bias on V0 to V5 pins of JBT6K47-AS. * Grayscale data and output voltages The output voltage is determined by the grayscale data value and six reference analog voltage inputs (V0 to V5). It equally divides g correction voltage using 6 bits grayscale data and converting D/A. wIN5 (MSB) wIN4 wIN3 wIN2 wIN1 W = X, Y, Z Grayscale Data 00H to 0CH 0DH to 14H 15H to 2DH 2EH to 36H 37H to 3FH Function Divide V0-V1 equally into 40, and output voltage. Divide V1-V2 equally into 8, and output voltage. Divide V2-V3 equally into 25, and output voltage. Divide V3-V4 equally into 9, and output voltage. Divide V4-V5 equally into 38, and output voltage. R2 12 2002-01-30 JBT6K47-AS * Grayscale data and output voltages (At 6-bit mode) GDn5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 GDn4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GDn3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 GDn2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 GDn1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 GDn0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 V0 V1 + (V0 - V1) 17/40 V1 + (V0 - V1) 23/40 V1 + (V0 - V1) 27/40 V1 + (V0 - V1) 30/40 V1 + (V0 - V1) 31/40 V1 + (V0 - V1) 33/40 V1 + (V0 - V1) 34/40 V1 + (V0 - V1) 35/40 V1 + (V0 - V1) 36/40 V1 + (V0 - V1) 37/40 V1 + (V0 - V1) 38/40 V1 + (V0 - V1) 39/40 V1 V2 + (V1 - V2) 1/8 V2 + (V1 - V2) 2/8 V2 + (V1 - V2) 3/8 V2 + (V1 - V2) 4/8 V2 + (V1 - V2) 5/8 V2 + (V1 - V2) 6/8 V2 + (V1 - V2) 7/8 V2 V3 + (V2 - V3) 1/25 V3 + (V2 - V3) 2/25 V3 + (V2 - V3) 3/25 V3 + (V2 - V3) 4/25 V3 + (V2 - V3) 5/25 V3 + (V2 - V3) 6/25 V3 + (V2 - V3) 7/25 V3 + (V2 - V3) 8/25 V3 + (V2 - V3) 9/25 V3 + (V2 - V3) 10/25 Output Voltage Grayscale Data 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH n = R, G, B 13 2002-01-30 JBT6K47-AS Grayscale Data 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH GDn5 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GDn4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GDn3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 GDn2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 GDn1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 GDn0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Output Voltage V3 + (V2 - V3) 11/25 V3 + (V2 - V3) 12/25 V3 + (V2 - V3) 13/25 V3 + (V2 - V3) 14/25 V3 + (V2 - V3) 15/25 V3 + (V2 - V3) 16/25 V3 + (V2 - V3) 17/25 V3 + (V2 - V3) 18/25 V3 + (V2 - V3) 19/25 V3 + (V2 - V3) 20/25 V3 + (V2 - V3) 21/25 V3 + (V2 - V3) 22/25 V3 + (V2 - V3) 23/25 V3 + (V2 - V3) 24/25 V3 V4 + (V3 - V2) 1/9 V4 + (V3 - V2) 2/9 V4 + (V3 - V2) 3/9 V4 + (V3 - V2) 4/9 V4 + (V3 - V2) 5/9 V4 + (V3 - V2) 6/9 V4 + (V3 - V2) 7/9 V4 + (V3 - V2) 8/9 V4 V5 + (V4 - V5) 1/38 V5 + (V4 - V5) 2/38 V5 + (V4 - V5) 3/38 V5 + (V4 - V5) 4/38 V5 + (V4 - V5) 6/38 V5 + (V4 - V5) 7/38 V5 + (V4 - V5) 10/38 V5 n = R, G, B 14 2002-01-30 JBT6K47-AS * Grayscale data and output voltages (At 4-bit mode) Output Voltage V0 V1 + (V0 - V1) 30/40 V1 + (V0 - V1) 35/40 V1 + (V0 - V1) 39/40 V2 + (V1 - V2) 4/8 V2 V3 + (V2 - V3) 4/25 V3 + (V2 - V3) 8/25 Grayscale GDn GDn GDn GDn Data 5 4 3 2 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Output Voltage V3 + (V2 - V3) 13/25 V3 + (V2 - V3) 17/25 V3 + (V2 - V3) 21/25 V3 V4 + (V3 - V4) 5/9 V4 V5 + (V4 - V5) 4/38 V5 Grayscale GDn GDn GDn GDn Data 5 4 3 2 00H 01H 02H 03H 04H 05H 06H 07H 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 n = R, G, B GDn1~0 = "L" * Grayscale data and output voltages (At 1 bit mode) Grayscale GDn Data 5 00H 01H 0 1 Output Voltage V0 V5 n = R, G, B GDn4 to 0 = "L" * Reference analog voltage inputs resistance ratio (R0 = 91.7 kW) R0 1.00 R1 0.11 R2 0.24 R3 0.10 R4 0.72 Note 5: Total resistance value is about 200 kW. * How to fix the grayscale data forcibly JBT6K47-AS is able to fix all the grayscale data to 63G/S despite the grayscale input by controlling the DW pin. The DW signal and output data timing is shown below. LOAD DW X01~X88 Y01~Y88 Z01~Z88 Normal data 63G/S 63G/S Normal data 63G/S Normal data 15 2002-01-30 JBT6K47-AS Timing Diagrams (1) DI/O, DO/I (Input) 0 CPH (Note 6) XIN0-5 XOR POL X01/X88 X02/X87 X03/X86 X87/X02 X88/X01 X01/X88 1 2 3 87 88 YIN0-5 XOR POL Y01/Y88 Y02/Y87 Y03/Y86 Y87/Y02 Y88/Y01 Y01/Y88 ZIN0-5 XOR POL Z01/Z88 Z02/Z88 Z03/Z88 Z87/Z02 Z88/Z01 Z01/Z88 DI/O, DO/I (Output) Note 6: Upper stage: X01 (R) U/D = High Lower stage: X88 (R) U/D = Low Timing Diagrams (2) 0 CPH 1 2 3 4 87 88 89 0 1 2 3 DI/O, DO/I (Input) DO/I, DI/O (Output) Grayscale data bus First data Last data First data LOAD X01 to X88 Y01 to Y88 Z01 to Z88 Hi-Z 16 2002-01-30 JBT6K47-AS Timing Diagrams (3) ex) Grayscale data and POL pins 0 CPH DI/O, DO/I (Input) wIN0 1 2 3 wIN1 wIN2 wIN3 wIN4 wIN5 POL w = X, Y, Z Importing the grayscale data wIN0' wIN1' wIN2' wIN3' wIN4' wIN5' w = X, Y, Z 17 2002-01-30 JBT6K47-AS Absolute Maximum Ratings (unless otherwise specified, VSS = 0 V, Ta = 25C) Characteristics Supply voltage Digital Analog Digital Input voltage Analog Reference analog voltage inputs voltage I/O Output voltage OUT Operating temperature Storage temperature VOUT2 Topr Tstg VINA V0~V5 VOUT1 Symbol DVDD AVDD VIND Rating -0.3 to 6.5 -0.3 to 6.5 -0.3 to DVDD + 0.3 -0.3 to AVDD + 0.3 -0.3 to AVDD + 0.3 -0.3 to DVDD + 0.3 -0.3 to AVDD + 0.3 -20 to 75 -55 to 125 Unit V V V V C C Note 7: The following shows the relative magnitude of each reference analog voltage: < < < < < < V0 < V1 < V2 = V3 = V4 = V5 or V5 < V4 = V3 = V2 = V1 < V0. V0 V5 = = = = Electrical Characteristics DC Characteristics unless otherwise specified, AVDD = 4.5 to 5.6 V, DVDD = 2.5 to 3.6 V, Ta = -20 to 75C Typical value is AVDD = 5.0 V, DVDD = 3.0 V, fCPH = 5 MHz, Ta = 25C Symbol DVDD AVDD V0 to V5 IIL IIH VIL 3/4 High level Low level Output voltage High level Output off current VOH IOFF VOUT1 VOUT2 Output voltage deviation Operating frequency VDO fCPH CL1 Output load capacity CL2 3/4 (Note 8) 30 pF 3/4 3/4 3/4 VIH VOL 3/4 3/4 3/4 IOL = 0.1 mA IOH = -0.1 mA (Note 12) Output VG1 to VG62 Output VG0, VG63 CL = 30 pF 3/4 3/4 0.1 0 -20 DC 3/4 Test Circuit 3/4 3/4 3/4 3/4 3/4 0 0.8 DVDD 0 DVDD - 0.5 Test Condition 3/4 3/4 (Note 11) Min 2.5 4.5 0 Typ. 3/4 3/4 3/4 Max 3.6 5.6 AVDD 1 1 0.2 DVDD DVDD 0.5 V DVDD 1 AVDD - 0.1 AVDD 20 5 30 mV MHz pF/pin CPH X01 to X88 Y01 to Y88 Z01 to Z88 mA X01 to X88 V Y01 to Y88 Z01 to Z88 DI/O, DO/I Unit V V V mA Characteristics Operating voltage (1) Operating voltage (2) Reference analog voltage inputs voltage Low level Input current High level Low level Input voltage Relevant Pin DVDD AVDD V0 to V5 (Note 9) V (Note 10) Output voltage range Note 8: 30 pF (min) must be connected to the selected grayscale level (incorporated amplifier) 18 2002-01-30 JBT6K47-AS DC Characteristics unless otherwise specified, AVDD = 4.5 to 5.6 V, DVDD = 2.5 to 3.6 V, Ta = -20 to 75C Typical value is AVDD = 5.0 V, DVDD = 3.0 V, fCPH = 5 MHz, Ta = 25C Symbol AIDD1 Current consumption (1) AIDD2 AIDD3 AIDDS DIDD1 Current consumption (2) DIDD2 DIDD3 DIDDS Standby current IDSTB 3/4 3/4 3/4 3/4 Test Circuit Test Condition (Note 13) (Note 14) (Note 15) (Note 16) (Note 13) (Note 14) (Note 15) (Note 16) Min Typ. 620 210 80 580 390 300 170 1 1 Max TBD TBD TBD TBD TBD TBD TBD TBD TBD mA mA mA AVDD Unit Characteristics Relevant Pin DVDD Note 9: XIN0-3, YIN0-3, ZIN0-3, DI/O, DO/I, CPH, LOAD, MD, GS, DW, U/D, Except test pins. Note 10: XIN0-3, YIN0-3, ZIN0-3, DI/O, DO/I, CPH, LOAD, MD, GS, DW, U/D, Except test pins. Note 11: V0 < V1 < V2 < V3 < V4 < V5 or V5 < V4 < V3 < V2 < V1 < V0. V0 V5 = = = = = = = = = = Note 12: AVDD = 5.5 V, fCPH = 5 MHz, 1 H = 64 ms, DI/O = "L" Note 13: DVDD = 3.3 V, AVDD = 5.5 V, fCPH = 5 MHz, 1 H = 64 ms, no load, checkerboard pattern, 6-bit mode Note 14: DVDD = 3.3 V, AVDD = 5.5 V, fCPH = 5 MHz, 1 H = 64 ms, no load, checkerboard pattern, 4-bit mode Note 15: DVDD = 3.3 V, AVDD = 5.5 V, fCPH = 5 MHz, 1 H = 64 ms, no load, checkerboard pattern, 1 bit mode Note 16: DVDD = 3.3 V, AVDD = 5.5 V, fCPH = 5 MHz, 1 H = 64 ms, no load, 6-bit mode, DI/O = "L" 19 2002-01-30 JBT6K47-AS AC Characteristics (1) unless otherwise specified, AVDD = 4.5 to 5.6 V, DVDD = 2.5 to 3.6 V, Ta = -20 to 75C Characteristics CPH Pulse width Enable setup time Enable hold time Enable high period Data setup time Data hold time LOAD setup time LOAD hold time LOAD High period 1 Output delay time 2 3 H L Symbol tCWH tCWL tsDI thDI tDIWH tsDD thDD tsLD thLD tLWH tpdDO1 tpdDO2 tpdDX tptdDX2 Test Circuit 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 CL = 10 pF CL = 10 pF CL = 30 pF CL = 30 pF 264 (Note 17, 18) Test Condition 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 (Note 18) (Note 18) (Note 17, 18) 5 30 8 0 1 1 200 12 ns 12 8 45 ms Min 20 20 15 0 1 ns ns CPH ns ns CPH CPH ns Typical vale is AVDD = 5.0 V, DVDD = 3.0 V, Ta = 25C Typ. Max Unit ns Note 17: Test circuit (1) When 1 output is selected: 30 kW Output pin Test pin 30 pF GND Note: Volume of probe and jig is included. Test circuit (2) When 264 output is selected: 30 kW/264 Output pin 30 pF 264 GND Note: Volume of probe and jig is included. Test pin Note 18: When the amplitude is 4 V and it reached at 90% level. 20 2002-01-30 JBT6K47-AS tCWH CPH VIH tpdDO1 DO/I, DI/O (Output) VIH tLWH LOAD tsLD VIH VIL DI/O, DO/I (Input) X01 to X88 Y01 to Y88 Z01 to Z88 wIN0~5 w = X, Y, Z VIH tpdDX/tpdDX2 Hi-Z tsDD Valid data VIH VIL thDD VIH VIL Invalid data VIH tsDI thDI tDIWH VIH thLD VIH VIL VIH tpdDO2 VIL tCWL VIL VIH VIL Valid data AC Characteristics (2) unless otherwise specified, AVDD = 4.5 to 5.6 V, DVDD = 2.5 to 3.6 V, Ta = -20 to 75C Typical value is AVDD = 5.0 V, DVDD = 3.0 V, Ta = 25C Characteristics DW setup time DW hold time Symbol tsDW thDW Test Circuit 3/4 3/4 Test Condition 3/4 3/4 Min 5 5 Typ. Max Unit ns ns LOAD VIH VIH tsDW DW thDW VIH VIL 21 2002-01-30 JBT6K47-AS RESTRICTIONS ON PRODUCT USE 000707EBM * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * Light striking a semiconductor device generates electromotive force due to photoelectric effects. In some cases this can cause the device to malfunction. This is especially true for devices in which the surface (back), or side of the chip is exposed. When designing circuits, make sure that devices are protected against incident light from external sources. Exposure to light both during regular operation and during inspection must be taken into account. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice. 22 2002-01-30 |
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